Studentski centar Pula
Ulica Sv. Mihovila 3
52 100 Pula
scpu@scpu.hr
Poslodavac - naručitelj posla | NEX NOVUS D.O.O. |
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OIB | 27018825320 |
Vrsta posla | FPGA junior/senior inžinjer (m/ž) |
Mjesto obavljanja posla | Remote, Pula, Zagreb, Split |
Predviđena cijena sata (min.) | 10,50 EUR |
Predviđena cijena sata (max.) | 21,00 EUR |
Putni trošak | Da |
Potreban broj studenata | 2 |
Period rada | Cijelogodišnji |
Radno vrijeme | fleksibilno (4-8 sati) |
Kontakt osoba | Ivan Projić |
Kontakt telefon | 099/600-1119
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Kontakt email | ivan@nex-novus.com |
Napomena | - What You’ll Be Doing? 2. Designing and optimizing dataflow architectures for high-speed, real-time processing under tight power and latency constraints 3. Collaborating with a small team of hardware, firmware, and AI engineers to bridge raw signal processing with algorithmic inference modules 4. Interfacing the FPGA platform with external processors (e.g. ARM or x86-based SoCs), via PCIe, MIPI CSI/DSI, or custom parallel protocols 5. Running experiments with different memory hierarchies (BRAM, external DRAM, FIFO buffers, etc.) to optimize for bandwidth, latency, and determinism 6. Supporting high-speed signal acquisition and processing of spatio-temporal data from vision and/or audio sensors 7. Iterating on your design based on real-world constraints—latency, jitter, throughput, thermals, and board-level integration - Who You Are? 1. A hands-on problem-solver with a deep interest in building efficient, real-time hardware systems 2. Curious and inventive, but rigorous about testing and validating your designs in a real-world context 3. Required Skills & Experience 4. Experience with Xilinx (preferred) or Intel/Altera toolchains (Vivado, Quartus, etc.) 5. Strong grasp of digital signal processing (DSP) concepts and experience with real-time data pipelines 6. Familiarity with hardware-software co-design principles (e.g. tightly coupling logic blocks to firmware or host software) 7. Experience working with asynchronous or time-coded data inputs 8. Deep understanding of pipelined and parallelized architectures 10. Proficiency in simulation, debugging, and optimization using tools like ModelSim, Logic Analyzers, and oscilloscopes - Bonus Points For: 2. Understanding of time-domain processing or biologically-inspired signal processing architectures 3. Experience with AXI, DMA, high-speed serial interfaces, or camera input protocols 4. Background in embedded AI or edge computing platforms 5. Experience integrating with microcontrollers (STM32, i.MX RT, etc.) or AI accelerators |